1. Field of the Invention
This invention generally relates to a semiconductor device and method for fabricating the same, and more particularly to a resistance random access memory (“RRAM”) device and method for fabricating the same.
2. Description of the Related Art
Colossal magneto resistive (“CMR”) thin films and oxidation thin films having Perovskite structure are resistance-reversible materials which can be applied to reversible switching process. For colossal magneto resistive thin film, when a positive impulse (voltage) is applied to it, its resistance is programmed to high resistance; when a negative impulse (voltage) is applied, its resistance is programmed to low resistance. For the oxidation thin film having Perovskite structure, when a positive impulse (current) is applied to it, its resistance is programmed to low resistance; when a negative impulse (current) is applied to it, its resistance is programmed to high resistance. Because of their resistance-reversible features, both materials can be applied to memory devices for resistance random access memory (“RRAM”). Furthermore, because the resistance will not change even after the power source has been disconnected, RRAM is a nonvolatile memory device.
FIG. 1 shows a cross-section of a conventional RRAM device. This RRAM device is a Type 1R1D (one resistor one diode) memory device. It includes a word line (N type region) 102 in substrate 100, a plurality of P+ regions 104 and N+ region 106, wherein word line 102 and P+ region 104 constitute a diode. A dielectric layer 114 is set on substrate 100. A plurality of memory units 107 are set in dielectric layer 114, wherein each memory unit 107 includes a bottom electrode 108, a top electrode 110, and a resistive film 112 between the bottom electrode 108 and the top electrode 110. Furthermore, there is a word line contact window 116 in dielectric layer 114. One end of word line contact window 116 is electrically connected to N+ region; the other end is electrically connected to a conducting line 120 on the surface of dielectric layer 114 so that the word line 102 can electrically connects with external circuits. Furthermore, there is a bit line 118 formed on dielectric layer 114 for electrically connecting with top electrode 110 of the memory unit 107.
FIG. 1 shows a cross-section of a conventional RRAM device. This RRAM device is a Type 1R1D (one resistor one diode) memory device. It includes a word line (N type region) 102 in substrate 100, a plurality of P+ regions 104 and N+ region 106, wherein word line 102 and P+ region 104 constitute a diode. A dielectric layer 114 is set on substrate 100. A plurality of memory units 107 are set in dielectric layer 114, wherein each memory unit 107 includes a bottom electrode 108, a top electrode 110, and a resistive film 112 between the bottom electrode 108 and the top electrode 110. Furthermore, there is a word line contact window 116 in dielectric layer 114. One end of word line contact window 116 is electrically connected to N+ region; the other end is electrically connected to a conducting line 116 on the surface of dielectric layer 114 so that the word line 102 can electrically connects with external circuits. Furthermore, there is a bit line 118 formed on dielectric layer 114 for electrically connecting with top electrode 110 of the memory unit 107.
Another conventional RRAM device Type 1R1T (one resistor one transistor) memory device is shown in FIG. 2. This memory device includes a plurality of N+ regions 202 and 204 in substrate 200, wherein N+ region is a common line. A dielectric layer 220 is set on substrate 200. Dielectric layer 220 includes a plurality of memory units 207, a plurality of gate structures (word lines) 212 and a plurality of contact windows 214 and 216. Each memory unit includes a bottom electrode 206, a top electrode 208 and a resistive film 210; each memory unit is set on the surface of each N+ region. Gate structure 212 and N+ regions 202 and 204 constitute a transistor. Contact windows 214 and 216 are electrically connected to the gate structure 212 and the common line 204 respectively so that the gate structure 212 and the common line 204 can connect with the external circuits. Furthermore, there is a bit line 218 formed on dielectric layer 220 for electrically connecting with the top electrode 208 of the memory unit 207.
Type 1R1T RRAM uses the transistor to easily control the reading/programming operations of the memory device. However, the size of Type 1R1T RRAM is too big. If F represents the critical dimension (“CD”), the minimum size of Type 1R1T RRAM is 6 F2.
For Type GRAD RRAM, the minimum size is 4 F2, which is smaller than Type 1R1T RRAM. Hence, Type 1R1T RRAM has a higher integration density. Type 1R1T RRAM uses the diode to control the reading/programming operations. Because the diode only allows to be turned on in one direction, the data in the memory device cannot be erased or reset after being programmed.